1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and, particularly, a system LSI on which a memory is mounted. More particularly the invention relates to a configuration of a test interface circuit for conducting an operation test of a memory in the system LSI.
2. Description of the Background Art
A system LSI such as a logic-merged DRAM obtained by integrating a memory core such as a large-capacity dynamic random access memory (DRAM) and a logic device such as a processor or ASIC (Application Specific Integrated Circuit) on the same semiconductor chip (semiconductor substrate) has been developed. Such a system LSI can realize high data transfer speed which is higher than that of a general DRAM by one or two digits by connecting the logic device and the memory such as a DRAM to each other via an internal data bus having a wide data bit width of 128 to 512 bits.
The DRAM and the logic device are connected to each other via an internal wire, and the internal wire is sufficiently short as compared with a wire on the board and has a small parasitic capacitance. Consequently, large reduction in charging/discharging currents in the internal wire and high-speed signal transmission can be realized. The number of external pin terminals of the logic device can be reduced as compared with a method of connecting an external general DRAM to a logic device. For the reasons, the system LSI such as a logic-merged DRAM greatly contributes to higher performance of information equipment dealing with a large amount of data in a three-dimensional graphics process, image/voice processes, and the like.
In the system LSI such as a logic-merged DRAM, only the logic device is mounted to a terminal via a pad. In the case of conducting an operation test on a memory such as a built-in DRAM, the test has to be carried out via the logic device. In this case, however, the control of the operation test is performed by the logic device, so that a load on the logic device increases. Specifically, in the case of conducting the operation test via the logic device, the following need arises. A command to conduct the operation test on the memory such as a DRAM is given from the outside to the logic device, a control signal for conducting the operation test is supplied from the logic device to the memory, and the test result is outputted to the outside by the logic device.
The operation test on the memory in the system LSI as a logic-mounted DRAM is therefore conducted via the logic device. It is consequently difficult to carry out a test of an operation timing margin or the like on the memory with high accuracy.
From the viewpoint of a program capacity as well, the number of test patterns generated by the logic device is limited, so that a sufficient operation test cannot be conducted. Due to the factors, it is difficult to sufficiently guarantee the reliability of the memory such as a DRAM. When the gate scale increases, a defect occurrence probability of the logic device itself becomes high, so that the reliability of the memory test deteriorates. Consequently, a need for conducting a test directly on the memory such as a DRAM from the outside by a dedicated tester such as a memory tester arises. Such a test is also called a direct memory access test.
FIG. 16 is a diagram schematically showing the configuration of a conventional DRAM-mounted system LSI 900.
Referring to FIG. 16, the system LSI 900 includes: a large-scale logic LG which is coupled to an external pin terminal group LPGA and executes an instructed process; an analog core ACR which is coupled between the large-scale logic device LG and an external pin terminal group APG and performs a process of an analog signal; a DRAM core MCR which is coupled to the large-scale logic LG device via internal wires and stores data necessary for the large-scale logic device LG; and a test interface circuit TIC which disconnects the large-scale logic device LG and the DRAM core MCR from each other and couples an external memory tester to the DRAM core MCR via a test pin terminal group TPG at the time of an operation test. The DRAM core MCR receives a power supply voltage VCC via a power supply pin terminal PST.
The analog core ACR includes a phase locked loop (PLL) circuit for generating an internal clock signal, an analog-to-digital converter for converting an analog signal from the outside into a digital signal, and a digital-to-analog converter for converting a digital signal supplied from the large-scale logic LG to an analog signal and outputting the analog signal.
The DRAM core MCR is a synchronous DRAM (SDRAM) which takes in an operation mode instruction signal and receives/transmits data synchronously with a supplied clock signal.
The large-scale logic LG device includes a memory control unit for executing a process such as an image/voice information process and controlling an access to the DRAM core MCR.
As shown in FIG. 16, by providing the test interface circuit TIC, the DRAM core MCR is completely disconnected from the logic device (large-scale logic device LG), so that the DRAM core MCR can be directly accessed via the test pin terminal group TPG. Consequently, the DRAM core MCR can be controlled and monitored directly from the outside by a memory tester or the like. By providing the test interface circuit TIC, according to a direct memory access test, an operation test which is substantially the same as that conducted on a general DRAM (SDRAM) by using a conventional memory tester can be conducted.
FIG. 17 is a diagram showing the configuration of the test interface circuit TIC and its related portion illustrated in FIG. 16.
Referring to FIG. 17, the test pin terminal group TPG includes: a pin terminal for receiving a test clock signal TCLK; a pin terminal for receiving a test control signal TCMD which designates a test operation mode; a pin terminal for receiving a test address TAD which designates a memory cell to be accessed in the DRAM core MCR in a test mode; a pin terminal for receiving write data (test input data) TDin at the time of an operation test; and a pin terminal for receiving test output data TDout from the test interface circuit TIC at the time of an operation test.
Each of the test input data TDin supplied to the test interface circuit TIC and the test output data TDout outputted from the test interface circuit TIC is set to have a bit width of, for example, eight bits in a manner similar to a general DRAM.
The test interface circuit TIC includes a latch/command decoder 1 for performing data processes of taking in the test control signal TCMD, test address TAD, and test input data TDin supplied to the test pin terminal group TPG synchronously with the test clock signal TCLK, decoding the test control signal to an internal command (operation mode signal) so as to be issued to the DRAM core MCR, expanding the 8-bit test input data TDin to write data of 256 bits, and the like.
The test interface circuit TIC further includes: a mode register 2 for storing information such as column latency of the DRAM core MCR; a CA shifter 3 for generating a read data selection signal RD_S by shifting a read selection signal supplied from the latch/command decoder 1 in accordance with the column latency information stored in the mode register 2; and a read data selection circuit 4 for performing 256:8 test output data selection of selecting 8-bit data from 256-bit data read from the DRAM core MCR in accordance with the read data selection signal RD_S from the CA shifter 3.
As test peripheral circuits, provided are: a selector 5 for selectively coupling the DRAM core MCR to one of the large-scale logic device and the test interface circuit TIC in response to a test mode instruction signal TE; a gate circuit 6 which receives a clock signal CLK supplied from, for example, the large-scale logic device in an ordinary operation mode and the test clock TCLK supplied at the time of the operation test and supplies an operation clock signal DCLK to the DRAM core MCR; and a gate circuit 7 for transmitting 256-bit read data RD read from the DRAM core MCR to the test interface circuit TIC when the test mode instruction signal TE is activated.
The 256-bit read data RD read from the DRAM core MCR is supplied to the large-scale logic device not through the selector 5 in order to supply the read data to the large-scale logic device at high speed at the time of the ordinary operation.
The DRAM core MCR takes in supplied data and signals and outputs the read data RD synchronously with the operation clock signal DCLK outputted from the gate circuit 6.
FIG. 18 is a diagram more specifically showing the configuration of the latch/command decoder illustrated in FIG. 17.
Referring to FIG. 18, the latch/command decoder 1 includes: a latch circuit 1a for taking in and latching the test control signal TCMD, the test address TAD, and the test input data TDin which are supplied to the test pin terminal group TPG in response to the rising edge of the test clock signal TCLK; a command decoder 1b for receiving and decoding a predetermined bit in the test control signal TCMD and the test address TAD from the latch circuit 1a and generating a command of designating an operation mode; a bit width expanding circuit 1c for expanding the 8-bit test input data TDin from the latch circuit 1a to 256-bit write data; and a latch circuit 1d for taking in and latching output signals of the command decoder 1b and the bit width expanding circuit 1c in response to the trailing edge of the test clock signal TCLK.
A test command TIFCMD, a test interface address TIFAD, and test input data TIFDin are outputted from the latch circuit 1d and are supplied to the DRAM core MCR via the selector 5. A command from the command decoder 1b is also supplied to the mode register 2. When a mode register set mode is designated, an address bit, test data, or the like is stored into the mode register 2.
As described above, the latch circuit 1a enters a latch state (or a through state) in response to the rising edge of the test clock signal TCLK. The latch circuit 1d enters a latch state (or a through state) in response to the falling edge of the test clock signal TCLK so as to be complementary to the latch circuit 1a. 
The command decoder 1b receives the test control signal TCMD and a predetermined address bit and generates an internal command for designating an operation mode, a row active command ACT, a bank precharge command PRE, a write command WRITE, a read command READ, an auto refresh command REFA, and the like.
FIG. 19 is a timing chart for explaining operations of the test interface circuit shown in FIG. 17.
As shown in FIG. 17, the DRAM core MCR transfers write data INDin and read data RD via different buses. As for the test pin terminal group TPG as well, the test input data TDin and the test output data TDout at the time of a test is transferred via different pin terminals. It is assumed here that a test instruction to the DRAM core is supplied from an external memory tester.
An operation of reading data from the DRAM core at the time of an operation test will be described first.
Referring to FIG. 19, in dock cycle #1, in order to instruct the DRAM core MCR to read data, the test control signal TCMD for generating the read command (reading operation instructing signal) READ is supplied. The test control signal TCMD supplied in clock cycle #1 is supplied as an internal command INCMD indicative of the read command READ from the test interface circuit TIC via the selector 5 to the DRAM core MCR.
At the time of the operation test, the selector 5 disconnects the large-scale logic device and the DRAM core MCR in accordance with the test mode instruction signal TE, selects the test interface command (test operation mode instructing signal) TIFCMD, the test interface address TIFAD, and the test interface input data TIFDin outputted from the test interface circuit TIC and transfers them to the DRAM core MCR.
The gate circuit 7 transmits the data RD read from the DRAM core MCR to the test interface circuit TIC in accordance with the test mode instruction signal TE. The DRAM core MCR reads internal data in accordance with the internal address INADD which is simultaneously supplied synchronously with the operation clock signal DCLK sent from the gate circuit 6. When column latency CL of the DRAM core MCR is equal to two clock cycles (in the following, such a case will be also simply described as xe2x80x9cin the case of CL=2xe2x80x9d), in accordance with the internal read command READ (INCMD) supplied in the clock cycle #2, effective read data is outputted at the rising edge of the test clock signal TCLK in clock cycle #4.
In the test interface circuit TIC, the CA shifter 3 shifts the read data selection signal RD_S generated from the upper five bits of the column address included in the test address TAD for a period of the clock cycles of the column latency CL in accordance with the test clock signal TCLK. When the read data selection signal RD_S is generated from the test address TAD, delay time in the test interface circuit TIC is included in accordance with the shift period. The delay time is written as xe2x80x9cTIC delayxe2x80x9d in FIG. 19.
At a timing when the 256-bit read data RD from the DRAM core MCR arrives at the read data selection circuit 4 via the gate circuit 7, that is, in clock cycle #4, the read data selection signal RD_S from the CA shifter 3 also enters a valid state. In response to this, the read data selection circuit 4 selects 8-bit data in accordance with a read data selection signal RD_S ( less than 0 greater than ) from the 256-bit data and transmits the selected data as test output data TDout (D00) to a pin terminal.
An operation of writing data to the DRAM core at the time of the operation test will now be described.
In dock cycle #2, the test control signal TCMD indicative of writing of data is supplied from an external memory tester to the DRAM core MCR. The test control signal TCMD is decoded to the write command (operation mode instruction signal) WRITE indicative of writing of data by the latch/command decoder 1. When the write command is supplied, the test input data TDin(DA) is also simultaneously supplied to the test pin terminal group TPG. The write command WRITE and the test write data DA are also transferred synchronously with the test clock signal TCLK in the test interface circuit TIC.
In the latch/command decoder 1, the 8-bit test input data DA (TDin) is converted to the 256-bit internal write data DAin by the bit width expanding circuit 1c. That is, an 8-bit data line is expanded and developed to a 256-bit data line.
Further, the test control signal TCMD to be decoded to the read command READ for instructing reading of data is supplied from the external memory tester in clock cycle #3. In the following clock cycle #4, a test control signal to be decoded to the write command WRITE for instructing writing of data is supplied.
In this case, in clock cycle #5, internal write data DBin is supplied to the DRAM core MCR. In clock cycle #6, the 256-bit data Dout is read from the DRAM core MCR and 8-bit read data D01 selected in accordance with a read data selection signal RD_S( less than 1 greater than ) by the read data selection circuit 4 is outputted as the test output data TDout from the test pin terminal group TPG.
The mode register 2 stores data indicative of the number of clock cycles of the TIC delay (one clock cycle in FIG. 19) and the column latency CL. The CA shifter 3 performs a shifting operation in accordance with the test clock signal TCLK for a period corresponding to the data stored in the mode register 2, thereby enabling the data RD read from the DRAM core MCR to be selected at an accurate timing and the test output data TDout to be outputted.
By providing the test interface circuit TIC as described above, the DRAM core MCR can be directly accessed from an external memory tester, so that the direct memory access test can be conducted. The operation test necessary for the DRAM core MCR provided in the system LSI can be therefore conducted by using a general SDRAM memory tester.
There is also a system LSI on which a plurality of memory cores having different memory capacities, data buses, column latencies, and operation frequencies are mounted. An example is a three-dimensional graphics LSI on which not only a main memory but also a frame buffer memory used as a work memory of a rendering machine, a Z buffer memory used for hidden-surface removal, and the like are mounted.
On each of the plurality of memory cores on such a system LSI, an independent operation test which is a direct memory access test via the test interface circuit TIC provided for each of the memory cores can be carried out.
In order to complete the operation tests on the plurality of memory cores, however, it is necessary to conduct the operation tests of the number corresponding to the number of memory cores. It causes a problem such that test time and the cost of the test accordingly increases.
It is an object of the invention to provide a configuration of a test interface circuit capable of conducting an operation test simultaneously on a plurality of memory cores (memory circuits) in a semiconductor integrated circuit device on which the plurality of memory cores are mounted.
The present invention is summarized as follows. The invention provides a semiconductor integrated circuit device comprising a plurality of memory circuits, a plurality of test interface circuits, and a high-order test interface circuit. Each of the plurality of memory circuits operates synchronously with an operation clock signal and executes a given operation instruction. The plurality of test interface circuits are provided in correspondence with the plurality of memory circuits, each for supplying an operation instruction as well as inputting and outputting test data to and from a corresponding one of the plurality of memory circuits in an operation test. The upper test interface circuit can supply an operation instruction based on a test operation instruction and input and output test data to each of the plurality of test interface circuits in the operation test. The upper test interface circuit includes a data comparing circuit for judging based on comparison among plural data outputted from the plurality of test interface circuits.
Therefore, a major advantage of the invention is that, since the operation instruction can be supplied and data can be received/transmitted simultaneously from/to the plurality of test interface circuits, an operation test simultaneously on the plurality of memory circuits as targets can be conducted.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.